The present subject matter relates to a semiconductor memory device, and more particularly, to a technology for reducing a total area of a memory device by changing a scheme of performing a data inversion operation.
A write data bus inversion (WDBI) function is used to reduce simultaneous switching output (SSO) noise by minimizing the change of data when the data is inputted to a memory device from a memory controller. The memory controller may be referred to as a chipset.
The memory controller sends such inversion information as WDBI together with the data to the memory device to thereby allow the memory device to judge whether the data is inverted or not.
FIG. 1 illustrates a configuration of a semiconductor memory device having a conventional 4 quarter bank structure.
Referring to FIG. 1, each of 4 banks BANK0 to BANK3 is divided into 4 sub-banks and the 4 sub-banks are disposed in 4 different quarters. For instance, the bank BANK0 is divided to 4 sub-banks having reference numerals 10, 50, 90 and 130. X around each of the banks represents a circuit for performing a row operation and Y around each of the banks represents a circuit for executing a column operation.
Moreover, CPERI shows a region in which circuits relating to a clock are disposed and DPERI shows a region in which circuits relating to data input/output are disposed.
FIG. 2 illustrates paths through which data are transmitted from data input circuits to banks.
Data are inputted in series through data pins of a memory device. Data pins DQ0 to DQ7 of the memory device include respective data input circuits 210 to 280. The data input circuits 210 to 280 align serially inputted data in parallel and transfer the aligned data to global lines GIO0<0:7> to GIO7<0:7>. In case that the memory device employs an 8-bit prefetch scheme, each of the data input circuits 210 to 280 aligns 8 data serially inputted through a corresponding one of the data pins DQ0 to DQ7 in parallel and the data input circuits 210 to 280 transmit the aligned data to the respective global lines GIO0<0:7> to GIO7<0:7>. That is, the data serially inputted through one data pin, e.g., DQ0 pin, are converted to aligned data and the aligned data are transferred onto 8 global lines, e.g., GIO0<0:7>. These global lines GIO0<0:7> to GIO7<0:7> are connected to Y blocks 11, 21, 31 and 41 of all of the banks 10, 20, 30 and 40.
In FIG. 2, there is illustrated only one quarter of the memory device having the quarter bank structure and thus all of the Y blocks 11, 21, 31 and 41 corresponding to the banks 10, 20, 30 and 40 are connected to the global lines GIO0<0:7> to GIO7<0:7> corresponding to the 8 data pins. Each of banks disposed in the rest of the quarters that are not shown in figures may be connected to its own global lines corresponding to its own 8 data pins. For instance, the banks 50, 60, 70 and 80 in FIG. 1 may be connected to global lines corresponding to data pins DQ8 to DQ15 that are not shown in figures.
An inversion information (WDBI) input circuit 290 receives inversion information WDBI through an inversion pin WDBI0 inputted from the memory controller and transfers the inversion information WDBI to the Y blocks 11, 21, 31 and 41 of the banks 10, 20, 30 and 40. Like the data, the inversion information WDBI is serially inputted through the inversion pin WDBI0, and the WDBI input circuit 290 aligns the serially inputted inversion information WDBI in parallel and transfers the aligned inversion information to the Y blocks 11, 21, 31 and 41 of the banks 10, 20, 30 and 40 through inversion lines WDBI<0:7>. One inversion pin per 8 data pins are disposed. In FIG. 2, there is illustrated the WDBI input circuit 290 that processes the inversion information WDBI of data inputted through the data pins DQ0 to DQ7.
In the Y blocks 11, 21, 31 and 41 of the banks 10, 20, 30 and 40, there are write drivers for transferring data on the global lines GIO0<0:7> to GIO7<0:7> to local lines LIO/LIOB in the banks 10, 20, 30 and 40. The write drivers invert or non-invert the data on the global lines GIO according to the inversion information WDBI and transfer the inverted or non-inverted data to the local lines LIO/LIOB. Each of the banks 10, 20, 30 and 40 includes the local lines LIO/LIOB whose number is the same as that of the global lines GIO. Moreover, each of the banks 10, 20, 30 and 40 includes write drivers corresponding to the number of the global lines GIO. For instance, the Y block 11 includes 64 write drivers.
FIG. 3 illustrates a block diagram of the data input circuit 210 illustrated in FIG. 2.
Referring to FIG. 3, the data input circuit 210 includes a data buffering unit 310, a data aligning unit 320 and a driving unit 330.
The data buffering unit 310 buffers data DATA_IN inputted through a data pad, which is a pad on a wafer connected to a data pin, and transfers the buffered data to the data aligning unit 320. Data are sequentially inputted to the data pad according to a prefetch scheme. In case of employing the 8-bit prefetch scheme, 8 data are continuously inputted in series in response to one write command.
The data aligning unit 320 aligns the serially inputted data in parallel. The number of data to be aligned in parallel is changed according to the number of bits processed by the prefetch scheme. For instance, in case of the 8-bit prefetch scheme, 8 data inputted in series are outputted in parallel through 8 lines GIO_PRE0<0:7>. Since the data inputted to the data aligning unit 320 are aligned and inputted on rising/falling edges of a data input clock WT_CLK, the data aligning unit 320 aligns the inputted data in parallel using the data input clock WT_CLK. FIG. 4 shows a data aligning process performed in the data aligning unit 320. Referring to FIG. 4, it is possible to more clearly understand the data aligning process.
The driving unit 330 loads the aligned data on GIO_PRE<0:7> onto the global lines GIO0<0:7>. The driving unit 330 is strobed by TDQSS_CLK and loads the data onto the global lines GIO0<0:7>. The TDQSS_CLK is a clock having a period corresponding to an interval between two write commands that are sequentially inputted.
FIG. 5 illustrates a block diagram of the inversion information (WDBI) input circuit 290 illustrated in FIG. 2.
Referring to FIG. 5, the WDBI input circuit 290 includes an inversion buffering unit 510, an inversion aligning unit 520 and a driving unit 530.
The inversion buffering unit 510 buffers inversion information WDBI_IN inputted through an inversion (WDBI) pad and transfers the buffered inversion information WDBI to the inversion aligning unit 520, wherein the WDBI pad is a pad on a die corresponding to an inversion pin. The inversion information WDBI_IN is continuously inputted in a series like data.
The inversion aligning unit 520 aligns in parallel the inversion information WDBI_IN inputted in series. The inversion aligning unit 520 aligns the buffered inversion information WDBI instead of the data and may have the same configuration as that of the data aligning unit 320. FIG. 6 illustrates an inversion information (WDBI) aligning process performed in the inversion aligning unit 520. Referring to FIG. 6, it is possible to more clearly understand the WDBI aligning process.
The driving unit 530 loads the aligned inversion information WDBI_PRE<0:7> outputted from the inversion aligning unit 520 onto inversion lines WDBI<0:7>. The driving unit 530 is strobed by TDQSS_CLK and loads the aligned inversion information WDBI_PRE<0:7> onto the inversion lines WDBI<0:7>.
FIG. 7 illustrates a circuit diagram of one of write drivers disposed in the Y block 11 of the bank 10.
There is an exclusive OR (XOR) gate 701 disposed at a front end of a write driver (WT_DRV) 702. The write driver 702 transfers an output of the XOR gate 701 onto local lines LIO_0<0> and LIOB_0<0>. The XOR gate 701 logically combines data on a global line GIO0<0> and inversion information WDBI<0>. Therefore, if the inversion information WDBI<0> has a logic low level, the data on the global line GIO0<0> is directly transferred onto the local lines LIO_0<0> and the LIOB_0<0>. On the other hand, if the inversion information WDBI<0> has a logic high level, the data on the global line GIO0<0> is inverted and then the inverted data is transferred onto the local lines LIO_0<0> and the LIOB_0<0>.
As described above, in the conventional memory device, the write driver 702 reflects the inversion information on the data.
A write enable signal WTEN illustrated in FIG. 7 is a signal that is enabled in a write operation. Therefore, the write enable signal WTEN controls the write driver 702 to be inactivated in a read operation since, as is well known, the data on the local lines LIO/LIOB should be transferred onto the global line GIO through a sense amplifier in the read operation.
As shown above, in the conventional memory device, the write driver plays a part of reflecting the inversion information on the data. The number of write drivers disposed in the Y block is the same as that of the local lines included in each bank. Thus, in case that the memory device uses a 4-bank, x32, an 8-bit prefetch scheme, the number of write drivers becomes 1024. In this case, the number of exclusive logic gates used to perform the data inversion operation also becomes 1024. This increases a total area of the memory device and thus the current consumption required to perform the data inversion operation is also increased.
As a memory device goes to high-capacity, the number of banks thereof is getting increased and thus the number of write drivers is also increased in proportion to the number of banks. For instance, if the number of banks is 16, the required number of write drivers becomes 4096, which is 4 times the number of write drivers in case of including 4 banks, and thus the number of exclusive OR gates also becomes 4096. Therefore, as the memory device goes to high-capacity, there is a problem that the area of circuits required to perform the data inversion operation gradually increases.